1. Field
Example embodiments relate to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device, including applying both a dual silicide process and a dual stress process.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the line width of transistor gate electrodes becomes narrower, thereby increasing resistance of the gate electrodes. Also, as transistor source/drain junctions become thinner, gate electrode resistance increases. In order to increase the operating speed of semiconductor devices, reducing their resistance is beneficial. In order to reduce resistance of a gate electrode, the gate electrode is formed of a polysilicon layer and a refractory metal silicide layer. Also, in order to reduce resistance of a source/drain region, a refractory metal silicide layer is formed on the source/drain region. For this, a refractory metal is deposited on a polysilicon gate electrode and a source/drain region, and then a silicide is simultaneously formed on both the gate electrode and the source/drain region.
However, when a silicide is formed, thicknesses of silicides of a source/drain region and a gate region of an NMOS region and a PMOS region vary depending on the structures of an active region and a polysilicon gate electrode of the NMOS region and the PMOS region. Thus, resistance Rs varies in the NMOS region and the PMOS region. Also, a silicide may grow in an edge portion of the active region according to the shape of the edge portion of a device isolation layer, and the silicide may cause junction leakage. Because the shape of the edge portion of the device isolation layer in the PMOS region and the NMOS region may vary, excessive growth of the silicide may occur in any region of the PMOS region and the NMOS region. Also, excessively grown silicide may affect resistance Rs of the silicide when critical dimensions (CDs) of an active region and a gate electrode are relatively small, while insignificantly affecting resistance Rs when CDs thereof are relatively large. Thus, the resistance Rs varies depending on the CDs. In order to overcome this problem, a dual silicide process for differently forming a silicide in an NMOS region and a PMOS region may be used.
Furthermore, after the dual silicide process, a stress is applied to a field effect transistor (FET), characteristics of the FET may be improved. A tensile stress increases electron mobility, and a compressive stress increases hole mobility. Accordingly, a tensile stress is applied to a channel of a transistor of an NMOS region to increase electron mobility, thereby increasing drain current of an N-type transistor. Also, a compressive stress is applied to a channel of a transistor of an PMOS region to increase hole mobility, thereby increasing drain current of a P-type transistor.